LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Dummy_TABLE
-- 
-- Inputs:
-- clk = The clock.
-- reset = The reset signal.
-- FWD_to_TBL_ACK = A request for table to process something for us
-- FWD_to_TBL_desAddress = The destination request of the packet we want info on
-- FWD_to_TBL_srcPort = The port that we received the packet on
-- FWD_to_TBL_srcAddress = The address that the packet we want info on came from
--
-- Outputs:
-- TBL_to_FWD_ACK = Table has received our request, now processing.
-- TBL_to_FWD_Valid = Table has our port and is returning it this cycle
-- TBL_to_FWD_Port = Table's response to our request (000 = port 0, ... 111 = unknown)
--
-- This is a dummy TABLE for testing purposes. It sends us ACKs the cycle after we ACK it, and then pretends to process
-- data for four cycles before telling us it's found our port. To see how it works in a waveform, see 
-- Dummy_TABLEoperation_timing.png.
--
-- This is up to date with the Table team's interface

ENTITY Dummy_TABLE IS
   PORT(
	   clk, reset			    : IN STD_LOGIC;
	   IN_FWD_to_TBL_ACK	    : IN STD_LOGIC;
	   IN_FWD_to_TBL_desAddress : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	   IN_FWD_to_TBL_srcAddress : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	   IN_FWD_to_TBL_srcPort	: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	   OUT_TBL_to_FWD_ACK		: OUT STD_LOGIC;
	   OUT_TBL_to_FWD_Valid		: OUT STD_LOGIC;
       OUT_TBL_to_FWD_Port	 	: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
       );
END Dummy_TABLE;

ARCHITECTURE dummy_table_arch OF Dummy_TABLE IS

COMPONENT One_Bit_Register IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		shiftout		: OUT STD_LOGIC 
	);
END COMPONENT;

COMPONENT Three_Bit_Counter_Prototype IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		cnt_en		: IN STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
	);
END COMPONENT;

SIGNAL count_enable: STD_LOGIC;
SIGNAL counter_output: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

-- Such a great algorithm.
OUT_TBL_to_FWD_Port <= "100";

-- Echo whatever FWD says in the next clock cycle. Don't ACK me until I tell you I'm done or
-- I'm going to send you another message.
Echo: One_Bit_Register PORT MAP (reset, clk, IN_FWD_to_TBL_ACK, OUT_TBL_to_FWD_ACK);

-- Count to four after each time FWD ACKs, then stop.
count_enable <= (NOT(counter_output(2)) AND NOT(reset)AND(count_enable OR IN_FWD_to_TBL_ACK));
IncrementCounter: Three_Bit_Counter_Prototype PORT MAP ((reset OR IN_FWD_to_TBL_ACK), clk, count_enable, counter_output);

-- Return a message end signal four clock cycles after I receive a request from FWD.
DoneCounting: OUT_TBL_to_FWD_Valid <= counter_output(2);
   
END dummy_table_arch;